[NTLUG:Discuss] Re: pci-e and linux ( and radeon -vs- nvidia ? - IC v. Board RAM

[Bryan J. Smith]

From:  Chris Cox 
> Another example:
> My XFX 6600GT AGP card used 256M chips...

Do you mean it actually has a total of 256M_Byte_?
Or do you mean it has 256M_bit_ ICs?

If you mean the former, I'll discuss that under your next comment.
If you mean the latter, understand that is just the _bit_ size of the IC.
(4) 256Mbit IC = 128MBytes.

There are other details as well.
But you have to understand how memory controller logic works to understand.
E.g., users that have issues when they only get 128MB of RAM when they insert a 256MB DIMM.

> yet they wired it for just 128M (for example).

Again, assuming you truly have 256MB of _total_ RAM,
it may have nothing to do with the wiring.
The NV43 IC may not support addressing more than 128MB.

Or there could be a variety of reasons.
Typically these are limitations of the memory controller (which is on  GPU).
E.g., the memory controller typically supports _only_ a _fixed_ set of IC widths and Mbit techologies.
And then only in _specific_ combinations.
E.g., a card might support 16 or 32-bit by 16Mbit or 32Mbit ICs, but only (4) 16bx32Mbit, (4) 32bx16Mbit, but not (2) 32bx32Mbit or (8) 16bx16Mbit.
And the latter might work but just only use the first 128MB total, even for all chips.

But I seriously doubt XFX would do this.
Unless, of course, it is cheaper for them to buy the same batch of ICs in quantity for _all_ cards,
even if only half the width/size if used when connected to the NV43/6600 controller.

But even in that case,
memory logic cannot be "modded."
XFX would not include extra ICs as that adds cost.
Again, they would only use ICs where all the width or size was not used by the memory controller.

E.g., not having seen the 6600	in person yet, let's assume it requires (8) ICs of 16-bit width for 128MB.
Normally a 8Mbit (x16b = 128Mbit) IC would be used to get 128MB.
Also note the datapath is 128-bit.

But let's say it's cheaper for XFX to buy 32b (x16Mbit = 256Mbit) modules in quantities of a quarter million than 16b and 32b in quantities of 100K.
So it uses (8) 8Mbit (x32b = 256Mbit) on both the NV43/6600 and NV40/6800 series.
The 6800 reports 256MB while the 6600 reports 128MB.
Why?
Because the former supports all 32b wide IC traces to 8 ICs (256-bit datapath) while the other supports only 16b (128-bit).
So why doesn't the 6600 just use (4) 32-bit ICs for 128b datapath and 128MB and save using 4 more chips?
Could be because of two reasons in the NV43/6600..
One is that 4x32b is not supported by the memory controller, only 4x16 (64b/64MB version) or 8x16 (128b/128MB version).
The other could be that 256Mbit ICs (such as 32x16) are not supported by the memory controller, and that would result in a measly combo (64b/128MB).
In fact, that latter combination might be what the cheaper 6200 or 6600 (non-GT) uses with a 64-bit datapath.

BIG NOTE:  This is NOT ACTUAL NV4x design/layout info.
I have NOT yet researched the memory controller support if the NV4x models.
It is merely a _very_small_subset_ of endless design/layout considerations in products.
Again, why?
Because of inherent limitations of _memory_controllers_.
The more flexibility, the more complex the logic (and number to transistors/traces) the memory controller is.

> Might be a difficult mod :)

You can't mod memory logic in the IC.
But 99.9% of enthusiasts don't understand how memory controllers work.

Like the guy who moved his 256MB DIMM from a i440BX to a i810 and it didn't work at all.
Then he tried his 256MB from his i810 in the i440BX and got only 64MB.

> Of course many are modding their 6800's
> (plain ones) to have all of
the pipelines enabled.

That is totally different.
You're talking about the _same_ NV40 GPU.
The pipes, memory controllers, etc... will be the same.
But the NV43 GPU is a different design.

nVidia tests for heat and timing tolerances.
Based on what unit pass and fail, they modify the PCB and/or firmware to disable those components.
Re-enable them at your own risk.

> Just as long as they are prepared to deal
> with any consequences that might result.

Correct, at least one of the units was disabled for a reason.
And enabling an odd number of pipes might actually reduce performance in timing,
versus having less pipes.

But the NV43/6600 is not a NV40/6800 with pipes disabled.
At least not at the PCB/firmware level.

-- 
Bryan J. Smith (currently mobile)
b.j.smith at ieee.org